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| IN74ACT112 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. * TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A; 0.1 A @ 25C Outputs Source/Sink 24 mA * * * * ORDERING INFORMATION IN74ACT112N Plastic IN74ACT112D SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Set L H L H H H H H H H Reset H L L H H H H H H H Inputs Clock X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q Q H L L H L* L* No Change L H H L Toggle No Change No Change No Change PIN 16=VCC PIN 8 = GND L H * Both outputs will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously X = Don't Care 1 IN74ACT112 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA 20 IOUT DC Output Sink/Source Current, per Pin mA 50 ICC DC Supply Current, VCC and GND Pins mA 50 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C 260 TL Lead Temperature, 1 mm from Case for 10 C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TJ Junction Temperature (PDIP) TA Operating Temperature, All Package Types IOH Output Current - High IOL Output Current - Low t r, tf Input Rise and Fall Time * VCC =4.5 V VCC =5.5 V (except Schmitt Inputs) * VIN from 0.8 V to 2.0 V Min 4.5 0 Max 5.5 VCC 140 +85 -24 24 10 8.0 Unit V V C C mA mA ns/V -40 0 0 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74ACT112 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed VCC Limits Symbol Parameter Test Conditions V 25 C -40C to 85C VIH Minimum High- VOUT=0.1 V or VCC - 4.5 2.0 2.0 Level Input 0.1 V 5.5 2.0 2.0 Voltage VIL Maximum Low - VOUT=0.1 V or VCC - 4.5 0.8 0.8 Level Input 0.1 V 5.5 0.8 0.8 Voltage VOH Minimum High- IOUT -50 A 4.5 4.4 4.4 Level Output 5.5 5.4 5.4 Voltage * VIN= VIL or VIH 3.76 3.86 IOH=-24 mA 4.5 4.76 4.86 5.5 IOH=-24 mA VOL Maximum Low- IOUT 50 A 4.5 0.1 0.1 Level Output 5.5 0.1 0.1 Voltage * VIN= VIL or VIH 0.44 0.36 IOL=24 mA 4.5 0.44 0.36 5.5 IOL=24 mA IIN Maximum Input VIN=VCC or GND 5.5 0.1 1.0 Leakage Current 5.5 1.5 Additional Max VIN=VCC - 2.1 V ICCT ICC/Input VOLD=1.65 V Max IOLD +Minimum 5.5 75 Dynamic Output Current VOHD=3.85 V Min IOHD +Minimum 5.5 -75 Dynamic Output Current VIN=VCC or GND ICC Maximum 5.5 4.0 40 Quiescent Supply Current (per Package) * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Unit V V V V A mA mA mA A 3 IN74ACT112 AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Unit Symbol Parameter 25 C -40C to 85C Min Max Min Max fmax Maximum Clock Frequency (Figure 1) 145 125 MHz tPLH 1.0 14.0 1.0 15.0 ns Propagation Delay, Clock to Q or Q (Figure 1) tPHL tPLH Propagation Delay, Clock to Q (Figure 1) or Q 1.0 1.0 14.0 12.0 1.0 1.0 14.5 12.5 ns ns Propagation Delay, Set or Reset to Q or Q (Figure 2) Propagation Delay, Set or Reset to Q or Q (Figure 2) Maximum Input Capacitance tPHL 1.0 12.5 1.0 13.0 ns CIN 4.5 4.5 pF CPD Power Dissipation Capacitance Typical @25C,VCC=5.0 V 35 pF TIMING REQUIREMENTS(VCC=5.0 V 10%, CL=50pF, Input tr=tf=3.0 ns) Guaranteed Limits Symbol Parameter 25 C -40C to 85C tsu Minimum Setup Time, J or K to Clock 2.0 2.5 (Figure 3) th Minimum Hold Time, Clock to J or K 2.0 2.0 (Figure 3) tw Minimum Pulse Width, Clock (Figure 1) 5.0 6.0 tw Minimum Pulse Width,Set or Reset (Figure 5.5 6.0 2) trec Minimum Recovery Time, Set or Reset to 0 0 Clock (Figure 2) Unit ns ns ns ns ns 4 IN74ACT112 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform EXPANDED LOGIC DIAGRAM 5 |
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